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A31W33128 Series
Preliminary
Document Title LCD Controller-Driver Revision History
Rev. No.
0.0 0.1
LCD Controller-Driver
History
Initial issue Error correction: Pad assignment & Boot capacitor connection: C1+ C1C1- C1+ C2+ C2C2- C2+
Issue Date
March 13, 2000 December 7, 2000
Remark
Preliminary
PRELIMINARY
(December, 2000, Version 0.1)
AMIC Technology, Inc.
A31W33128 Series
Preliminary
Features
n Power supply range : 2.4V to 5.5V 2.7V to 11.0V (LCD drive) n Internal LCD drivers : 128 segment signal drivers 17 /33 commons signal drivers n Power save current (<1uA) n On chip 128 x 65 Display Data RAM n 8 BIT 80/68-Series Parallel interface ,Serial interface n Build-in RC oscillator or external clock input (18KHz) n n n n n n n n 1:4 / 1:5 / 1:6.7(default) Bias Ratio 1:2 to 1:4 Bias Ratio (external) 16 level internal contrast control Build-in temperature compensation circuit On chip internal DC/DC converter / External Power supply Dual/ Triple booster 2 internal Icon common Output systems TCP package, Gold bumps
LCD Controller-Driver
The A31W33128 is a CMOS LCD driver, which has 128 segment, and 17 or 33 common graphic display. It has 80/68-series 8 bit parallel and serial interface capability for operating with general CPU. The internal 65 x 128 display data RAM makes the display of both graphics and characters possible. Besides the general LCD driver features, it has on chip LCD bias divider circuit such that minimize external component required in system application.
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AMIC Technology, Inc
A31W33128 Series
Block Diagram
1. Block Overview
COMICN1,2 VDD V1 to V5
COM1 to 32
SEG1 to 128
LCD Driver
C1C1+ C2C2+ VOUT VCNT FNC1 FNC2 LCD Power Supply Circuit
Display Data Control
Data Latch
Data Input/ Output
Page Address Decode
Display RAM 8320 bits
Start Line Address Decoder
Start Line Register & Counter
Start Line Register
OSC1 OSC2
Oscillating Circuit
Column Address Decoder
Line Control
LCD Timing Circuit
Page Address Register
Column Address Register & Counter
Status Register
VSS Power on Reset
Command Decoder
MPU interface For 68-Series & 80-Series
D0 to D7
A0
P/S C68/80 CS
R/W
E
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A31W33128 Series
Block Diagram
2. LCD Power Supply Circuit Block Diagram
VOUT
VCNT
V5 C1C1+ C2C2+ Triple Booster & Double Booster Voltage Regular Bias Resister
Reference Regular
Adjustment Circuit V4 Voltage Follower V3 V2 V1 Command Register
CLK Reference Voltage
FCN1
FCN2
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A31W33128 Series
Pad Assignment
COM Output
TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 NC VDD VDD VDD VDD CS A0 R/W E P/S C68/80 OSCO OSCI VSS VSS VSS VSS NC D0 D1 NC D2 D3 NC D4 D5 NC D6 D7 NC FNC2 FNC1 VSS VSS VSS VSS TEST6 NC VOUT NC C2+ C2C1+ C1NC VCNT TEST7 TEST8 VDD VDD VDD VDD V1 V2 V3 V4 V5 TEST9 17 ICN1 2 4 6 8 10 12 14 16 1 3 5 7 9 11 13 15 SEG128 SEG127 SEG126 SEG125
Chip Identification Marks
Control Pins
(0,0)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(The identification marks are larger than the actual scaling)
(4096.5, 740) 50 50
50 50 Unit : um 50 50
50 50 (-4097.5, 740)
(The identification marks are made of AI patterns)
SEG5 SEG4 SEG3 SEG2 SEG1 18 20 22 24 26 28 30 32 19 21 23 25 27 29 31 ICN2
. Pad pitch Segment driver Comon driver Control pad . Gold bump size Drive Input pin . Gold bump height
65um 65um 120um 43x85um 72x85um 18um (Typ.)
COM Output
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AMIC Technology, Inc
A31W33128 Series
Pad Coordinates
Unit: m (The origin is the center of the chip)
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Pin Name TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 NC VDD VDD VDD VDD
CS
A0 R/W E P/S C68/80 OSCO OSCI VSS VSS VSS VSS NC D0 D1 NC D2 D3 NC D4 D5 NC D6 D7 NC FNC2 FNC1 VSS VSS VSS VSS TEST6 NC VOUT NC C2+ C2C1+ C1NC VCNT TEST7 TEST8 VDD VDD VDD VDD V1 V2 V3 V4 V5
X -3877.5 -3807.5 -3737.5 -3667.5 -3597.5 -3527.5 -3457.5 -3371.5 -3251.5 -3131.5 -3011.5 -2891.4 -2763.6 -2635.8 -2508 -2380.2 -2252.4 -2124.6 -1996.8 -1876.8 -1756.8 -1636.8 -1516.8 -1430.8 -1264.2 -999.8 -835.2 -670.6 -406.2 -241.6 -77 187.4 352 516.6 781 945.6 1049.2 1177 1298.7 1418.7 1538.7 1658.7 1744.7 1814.7 1900.7 1981.7 2062.7 2182.7 2302.7 2422.7 2503.7 2589.7 2675.7 2745.7 2831.7 2951.7 3071.7 3191.7 3311.7 3431.7 3551.7 3671.7 3791.7
Y -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5 -897.5
No. 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126
Pin Name TEST9 NC COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COMICN2 NC SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43
X 3877.7 4103.5 4103.5 4103.5 4103.5 4103.5 4103.5 4103.5 4103.5 4103.5 4103.5 4103.5 4103.5 4103.5 4103.5 4103.5 4103.5 4103.5 4103.5 4103.5 4127.5 4062.5 3997.5 3932.5 3867.5 3802.5 3737.5 3672.5 3607.5 3542.5 3477.5 3412.5 3347.5 3282.5 3217.5 3152.5 3087.5 3022.5 2957.5 2892.5 2827.5 2762.5 2697.5 2632.5 2567.5 2502.5 2437.5 2372.5 2307.5 2242.5 2177.5 2112.5 2047.5 1982.5 1917.5 1852.5 1787.5 1722.5 1657.5 1592.5 1527.5 1462.5 1397.5
Y -897.5 -717.5 -647.5 -577.5 -507.5 -437.5 -367.5 -297.5 -227.5 -157.5 -87.5 -17.5 52.5 122.5 192.5 262.5 332.5 402.5 472.5 548.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5
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A31W33128 Series
Pad Coordinates (continued)
Unit: m (The origin is the center of the chip)
No. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 Pin Name SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 X 1332.5 1267.5 1202.5 1137.5 1072.5 1007.5 942.5 877.5 812.5 747.5 682.5 617.5 552.5 487.5 422.5 357.5 292.5 227.5 162.5 97.5 32.5 -32.5 -97.5 -162.5 -227.5 -292.5 -357.5 -422.5 -487.5 -552.5 -617.5 -682.5 -747.5 -812.5 -877.5 -942.5 -1007.5 -1072.5 -1137.5 -1202.5 -1267.5 -1332.5 -1397.5 -1462.5 -1527.5 -1592.5 -1657.5 -1722.5 -1787.5 -1852.5 -1917.5 -1982.5 -2047.5 -2112.5 -2177.5 -2242.5 -2307.5 -2372.5 -2437.5 -2502.5 -2567.5 -2632.5 -2697.5 Y 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 No. 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 Pin Name SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 NC COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COMICN1 NC X -2762.5 -2827.5 -2892.5 -2957.5 -3022.5 -3087.5 -3152.5 -3217.5 -3282.5 -3347.5 -3412.5 -3477.5 -3542.5 -3607.5 -3672.5 -3737.5 -3802.5 -3867.5 -3932.5 -3997.5 -4062.5 -4127.5 -4103.5 -4103.5 -4103.5 -4103.5 -4103.5 -4103.5 -4103.5 -4103.5 -4103.5 -4103.5 -4103.5 -4103.5 -4103.5 -4103.5 -4103.5 -4103.5 -4103.5 -4103.5 -4103.5 Y 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 897.5 542.5 472.5 402.5 332.5 262.5 192.5 122.5 52.5 -17.5 -87.5 -157.5 -227.5 -297.5 -367.5 -437.5 -507.5 -577.5 -647.5 -717.5
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A31W33128 Series
Input/Output Pin Function
Pin No. 20-23, 39-42 8-11, 55-58 18 19 12 13 14 15 16 OSCO OSCI
CS
Symbol VSS VDD
Type Supply Supply Output Input Input Input Input Input Input GROUND Power supply pin Oscillator output Oscillator input Chip select input, low active A0=Low: Command input.
Description
A0 R/W E P/S
A0=High: Display data input and outputs 68-Series R/W=High: Read, R/W=Low : Write 80-Series : Write enable, Active Low 68-Series : Enable clock signal input, Active High 80-Series : Read enable, Active Low Parallel/serial interface select input High : 8-bit parallel interface Low : Serial interface 17 C68/80 Input Microprocessor interface select input High : 68-Series interface is selected Low : 80-Series interface is selected 25-26, 28-29, 31-32, 34-35 D0-7 Input/ Output 8bit bi-directional data bus to be connected to microprocessor's data bus P/S=High : 8-bit configuration data bus connection P/S=Low : Serial interface connection D0 Serial data input D1 Serial clock input D2 Serial data output 84-211 66-81 213-228 229 82 37 38 42 47 48 49 50 52 SEG1SEG128 COM1COM32 COMICN1 COMCN2 FNC2 FNC1 VOUT C2+ C2C1+ C1VCNT Input Input Output Input Input Input Input Input Output Output Output Provide the LCD segment driving signal Provide the LCD common driving signal Provide the Icon common driving signal COMICN1 and COMICN2 output the same phase waveform. LCD power control input pin LCD power control input pin Boosting voltage output 2nd-step boosting capacitor negative connection 2nd-step boosting capacitor positive connection 1 st-step boosting capacitor negative connection 1 st-step boosting capacitor positive connection LCD power supply voltage control
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A31W33128 Series
Input/Output Pin Function (continued)
Pin No. 59 60 61 62 63 1-7, 24, 27, 30, 33, 36, 43-44, 46, 51, 53-54, 64-65, 83, 212, 230 1 2 3 4 5 6 43 53 54 64 TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 TEST8 TEST9 NC Open No Connection Symbol V1 V2 V3 V4 V5 Type Input Input Input Input Input Description LCD driver bias voltage. They can be supplied externally or generated by the internal bias divider. 1: 4 bias 1: 5 bias 1: 6.75 bias V1 1/4 x V5 1/5 x V5 1/6.75 x V5 V2 2/4 x V5 2/5 x V5 2/6.75 x V5 V3 2/4 x V5 3/5 x V5 4.75/6.75 x V5 V4 3/4 x V5 4/5 x V5 5.75/6.75 x V5 * Inputs LCD drive bias voltage when using an external LCD power supply circuit. V5 V4, V3, V2, V1 > VSS
Open
Cannot be wired to the outside
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A31W33128 Series
Commands Table
Command A0 Set Display ON/OFF 0 E 1 Bit pattern Comment R/W D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 1 1 0 D0:0 Display OFF: Display goes out, regardless of the content of the display data RAM 1 D0:1 Display ON: Normal Display 0 0 1 Display start line address Sets the line address of the display data RAM output to COM1 0 1 0 1 1 Page Address Sets the page address of the display data RAM. Page 8 is assigned to the icon display 0 0 0 0 1 0 Upper 3 bits of Sets upper 3 bits of the display data RAM Column Column Address 0 1 0 1 0 1 0 0 0 0
Address Lower 4 bits of the Column Address
Set Display Start Line Page Address Set
0 0
1 1 1 1 0 1 0 1
Upper 3 bits of Column 0 Address Set Lower 4 bits of the Column Address Set Status Read Display Data Write Display Data Read ADC Select 0 0 1 1 0
Lower 4 bits of display data RAM column Address Status Read Writes data of D0 to D7 in the display data RAM Reads data from D0 to D7 from the display data RAM
Status Write Data in Display Data RAM Read Data from Display Data RAM 010000
0 1
Display Normal/Reverse Display All-Lit ON/OFF Duty Selection/ Alternate Common Output
0
1
0
1
0
1
0
0
1
1
0 1 0 1 0 1 1
0 0
1 1
0 0
1 1
0 0
1 1
0 0
0 1
1 0
0 * 0 1
Read Modify Write End Reset
0 0 0
1 1 1
0 0 0
1 1 1
1 1 1
1 1 1
0 0 0
0 1 0
0 1 0
0 1 1
0 0 0
Reverses upper or lower display data RAM column address D0:0 Normal: Column addresses 00 to 7FH correspond to segment outputs 1 to 128 D0:1 Reverse: Column addresses 00 to 7FH correspond to segment outputs 128 to 1 D0:0 Normal : "1" makes the display be lit D0:1 Reverse : "0" makes the display be lit The icon display is not reversed D0:0 Normal Display D0:1 Display All-Lit D0:0 1/17 Duty D0:1 1/33 Duty D1:0 Common output order: In a numerical order D1:1 Common output order: Alternate output to right and left of the chip. Increments display data RAM column address only during writing Read Modify Write Release. It does not affect the contents of the display data RAM. After resetting, display starts according to the reset value: 1.Resets the display start line register to the 1st line. 2.Resets the column address counter to address 0. 3.Resets the page address counter to page 0. 4.Clears the serial interface counter. 5.Turns OFF the Read Modify Write.
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A31W33128 Series
Commands Table (continued)
Command A0 Bias Selection 0 E 1 Bit pattern R/W D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 1 0 D1 D0 Comment D1,D0:0, 0 1/6.75 Bias Selection D1,D0:0, 1 1/5 Bias Selection D1,D0:1, 0 1/4 Bias Selection D1,D0:1, 1 Don't care Minimum value (default)
LCD Voltage Command Fine Adjustment Data
0
1
0
1
0
0
0
LCD Power Supply Circuit ON/OFF
0
1
0
0
0
1
0
Icon Only Display
0
1
0
1
1
0
0
Reference Voltage Temperature Coefficient Selection Power save
0
1
0
1
1
1
0
Maximum value D0: 0 LCD power supply circuit OFF D0: 1 LCD power supply circuit ON The LCD power supply circuit connected to pinsFNC1, FNC2 starts its operation earlier than the LCD POWER Supply circuit ON/OFF command. D2: 0 Normal Display 0 D2 Boosting Control D2: 1 Icon Only Display Boosting control data: Selects boosting Data Frequency 01* 0 D0:0 -0.13%/C 1 D0:1 +0.01%/ C
0 . 1 0
0 . 1 1
0 . 1 0
0 . 1 0 1
Display OFF, Display all-lit ON
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A31W33128 Series
Operation of LCD Display Driver
1. Powering ON setting sequence Recommended Command Setting Sequence: (1) Set Display OFF : In order to prevent unnecessary characters from being displayed during powering ON of the power . The state is changed to the " Power save mode" after turning on the Display All-Lit ON with the display OFF. (2) Set Display All-Lit OFF: Normal display operation and the oscillation start. (3) Set LCD Power Supply Circuit ON (4) Set Bias Select (5) Set Reference Voltage Temperature Compensation Coefficient (6) End Command Input (7) Set Duty Select/Alternate Common Output (8) Set Display Normal/Reverse : D0 : 0 Normal Display data "1" makes the display be lit. D0 : 1 Reverse Display data "0" makes the display be lit.
(9) Set Display Start Line address: Changing the display start line allows for page change on the display screen as well as vertical smooth scroll. (10) Common Output Sequence (11) Icon Only Display (12) Display Data Write: After writing the display data, the column address is automatically incremented. To write the display data in succession after setting the 1st column address to be written by the COLUMN ADDRESS SETTING command, the column address is not needed to be set each time. The icon display data is valid for only D0. Write "L" or data to be displayed in all display data RAM before turning the display ON. (13) Display ON 2. Set Powering OFF, Power Save Mode Set Powering OFF sequence: (1) Set Display OFF (2) Set LCD Power Supply Circuit OFF
Power Save Mode:
When in Power save mode, the command sleeps the system : * Internal oscillating circuit and LCD power supply circuit are stopped. * The Segment and Common outputs are fixed at VSS level. * The LCD display goes out. * The contents of the display data RAM, the command and the address before the power save mode do not change. Combination of Commands Display ON Display All-Lit OFF Display ON Display All-Lit ON Display OFF Display All-Lit OFF Display OFF Display All-Lit ON State Normal display operation All-lit display AII-OFF Power save
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3. MPU Interface Select The parallel 68-series, 80-series interface or serial interface can be selected by P/S, C68/80 pin setup:
P/S Pin H L
C68/80 Pin L H don't care
MPU Interface 80-series Interface selected 68-series Interface selected Serial Interface selected
3.1 MPU Parallel 68-Series and 80-Series Interface The parallel interface consists of 8 bi-directional data pins (D0-D7), R/W( WR ), A0, E(RD ), CS In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. A31W33128 Pin Name 68-Series MPU Signal 80-Series MPU Signal A0 A0 A0 E E R/W R/W
CS CS CS
D0 - D7 D0 - D7 D0 - D7
RD
WR
3.2 MPU Serial Interface The serial interface consists of serial clock input SCLK, serial data input SDI and output SDO, chip select CS , P/S, R/W, A0. When the E pin to be open and the serial interface is selected by setting P/S to "L", the instruction code is the same as for the parallel interface .By setting CS to "L". the serial interface circuit enters an operating state. And by setting CS to "H', it will reset the serial interface circuit and initialized the counter. Data is input in the order of D0, D1, D2,....D7. The displayed data and commands are written at the rising edge of the SCLK. But the displayed data and status are read at the falling edge of the SCLK. Data read needs a dummy read. When in reset condition, the SDO pin will be driven to "H", and the status reading will be invalidated. D0 (SDI) : Serial Data Input D1 (SCLK) : Serial Clock Input D2 (SDO) : Serial Data Output D3 to D7 : Open E : Open C68/80 : Open A0 L H L H 4. Command Execution When the input at D0-D7 is interpreted as a command and it will be decoded and written to the corresponding command register. The user can input the commands continuously without confirming the busy flag of status command register because the command is completely executed within the cycle time (tcyc) according to the timing characteristics of the command input. But that re-inputting the command within the executed cycle time is inhibited. R/W L H H L Operation Command input Display data read Status read Display data write
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5. Data Bus Select When CS is held at "H" level, the D0-D7 is in high impedance state. 68/80-Series shared A0 1 1 0 0 6. Display Data RAM The Display Data RAM is made of dual port RAM. The size of the RAM is 64 x 128 + 128 = 8320 bits. Write "L" or data to be displayed in all display data RAM before turning the display ON. 7. Accessing the Display Data RAM From MPU In order to match the operating frequency of Display Data RAM with that of the MPU, a dummy read is required before the first actual display data read. When the MPU reads the Display Data RAM, the first dummy read cycle stores the first read data in the bus holder, and then at the next read cycle the MPU read the first read data from the bus holder. It does not need a dummy cycle when MPU writes data to the Display Data RAM. When the MPU write data to Display Data RAM, once the data is stored in the bus holder, then it is written to Display Data RAM before the next data write cycle. 8. Set Column Address (higher, lower nibble) This command specifies the column address (higher and lower nibble) of the Display Data RAM. The column address will be incremented by each data access after it is pre-set by the MPU. 9. Set Page Address(0-8) This command positions the page address to 1 of 9 possible positions in Display Data RAM. Page 0-7 are the graphic display area, and the page 8 are the Icon display area. 10. Set display start line (0-63) The command is used to change the display page or smooth scroll. With the display start line value equals to 0, D0 of page 0 is mapped to COM1. The display start line values of 0 to 63 are assigned to page 0 to 7. 68-Series R/W 1 0 1 0 E 0 1 0 1 80-Series R/W 1 0 1 0 Description
Reads from Display Data RAM Writes to Display Data RAM Reads Status Command Write to internal register
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11. Status Read This command shows the status of A31W33128 =0 : The A31W33128 is not busy 1 : The A31W33128 is in internal operation or reset state. ADC : D6 =0 : ADC Reverse : Column addresses 00 to 7FH correspond to segment outputs 128 to 1. 1 : ADC Normal : Column addresses 00 to 7FH correspond to segment outputs 1 to 128. ON/OFF : D5 =0 : Display ON 1 : Display OFF RESET : D4 =0 : In normal operation state 1 : Internal reset operation state PSAVE : D3 =0 : In normal operation state 1 : In Power Save state ICON : D2 =0 : In normal operation state 1 : In Icon only display state DREV : D1 =0 : Display Normal 1 : Display Reverse ALON : D0 =0 : Normal display 1 : Display All-Lit ON When a serial interface is selected, the status read from the SDO pin is always high level during reset operation. 12. 1/33 ,1/17 Duty Select, Alternate Common Output Common Output sequence at duty 1/33 Output sequence 1 2 3 . . 16 17 . . 31 32 33 Common driving signal output in numerical COM1 COM2 COM3 . . COM16 COM17 . . COM31 COM32 COMICN1,2 Common driving signal Alternate Output COM1 COM17 COM2 . . COM9 COM25 . . COM16 COM32 COMICN1,2 BUSY : D7
Common Output sequence at duty 1/17 Output sequence 1 2 3 . . 15 16 17 Common driving signal output in numerical COM1,17 COM2,18 COM3,19 . . COM15,31 COM16,32 COMICN1,2
The common output at duty 1/17 only has in numerical sequence.
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13. Read Modify Write , END Read Modify Write This command puts the chip in read modify write mode. In this mode the column address is saved before entering the mode, and is incremented by display data write but not by display data read. During the Read Modify Write mode, all commands are usable except the Column address set command. End This command relieves the A31W33128 from read modify write mode. The column address that is saved before entering read modify write mode will be restored. 14. Boosting frequency select Select the boosting frequency: D1 0 0 1 1 15. RC Oscillator Circuit The built-in RC oscillator generates the clock for the boosting frequency, and is also used in the display timing. When using the external clock, the external clock is input to OSCI, and OSCO is left floating. Used built-in RC oscillator , Rf = 1 M Frame freq. 66.17 Hz at fosc = 18 KHz Frame freq.68.18 Hz at fosc = 18 KHz D0 0 1 0 1 Boosting Freq. Fosc/2 Fosc/4 Fosc/8 Fosc/16
1/17 duty 1/33 duty
16. Reference Voltage Temperature Compensation Coefficient Select This command is to set one out of 2 different temperature coefficients in order to match various liquid crystal temperature grades. VREF =
IVREF(T2)I - IVREF(T1)I T2 - T1
T2 > T1
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17. LCD Power Supply Circuit The LCD power supply circuit generates the LCD voltage needed for display output, which is controlled by pins FNC1 ,FNC2 and LCD power supply circuit ON/OFF command. It consists of: 1. Doubler/tripler DC-DC voltage converter. 2. Voltage regulator and LCD voltage command fine adjustment circuit. 3. LCD bias resistor and voltage follower FNC2 L H L H FNC1 L L H H Doubler/Tripler Circuit ON OFF OFF OFF Voltage Regulator Circuit ON OFF ON OFF LCD Bias Resistor/ Voltage Follower Circuit ON OFF ON ON
* FNC1 and FNC2 must connect to VDD or VSS. * Don't connect the external power supply with the built-in LCD power supply circuit ON, it may lead to a breakdown. 17.1 Doubler/Tripler It is the 2X, 3X DC-DC voltage converter. Please refer to application notes.
Triple VOUT = 9V Double VOUT = 6V VDD=3V
VSS
Example of Booster Output
17.2 LCD Voltage Adjustment There are two methods of adjusting the LCD voltage as follows: 17.2.1 Voltage Regulator Voltage regulator output V5 is adjusted by externally attached Ra and Rb.
Ra + Rb Ra
V5=
X VREF (V) + VREF
V5
Ra Rb
VCNT
VSS
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17.2.2 LCD Voltage Command Fine Adjustment control Software control of 16 voltage levels adjustment of V5 voltage by set 4 bits of the data bus. It can adjust the LCD contrast. 17.3 LCD Bias voltage When use built-in LCD bias resistor, Software can control the 1/6.7, 1/5,1/4 bias ratio to match the characteristic of LCD panel. 17.4 Voltage Follower The voltage follower buffers the LCD bias voltage created by the built-in bias resistor, and supplies it to the LCD drive circuit.
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Interface
1. Parallel Interface 1.1 Display Data Write ( the 80-Series interface)
R/W MP Data Bus Holder Internal Timing R/W Internal Busy Flag n n n+1 n+1 n+2 n+2 n+3 n+3
1.2 Display Data Read (the 80-Series interface)
R/W MP E
Data
N
X
Address set address N Dummy read
n
n+1
Data read address N Data read address N+1
R/W E
Internal Timing
Column address Bus Holder X
N n
N+1 n+1
N+2 n+2
Internal Busy Flag
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2 Serial Interface Serial Interface Display Data Write/Read Timing
CS A0 R/W D1 (SCLK) D0 (SDI) D2 (SDO) D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 D0 D0
A0 0 0 1 1
R/W 0 1 0 1
D0 (SDI) Command Write Invalid Data Write Invalid
D2 (SDO) Invalid Status Read Invalid Data Read (Note)
Note: Data Read needs a dummy read
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Display Data RAM vs Address Page Address
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0
Line Address
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H ADC D0= "0" ADC D0= "1"
An example of common output executing display start from line address 30H at 1/33 duty.
0, 0, 0, 0
Page0
0, 0, 0, 1
Page1
COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32
0, 0, 1, 0
Page2
0, 0, 1, 1
Page3
0, 1, 0, 0
Page4
0, 1, 0, 1
Page5
An example of common output executing display start from line address 30H at 1/17 duty. Display Start
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM1, 17 COM2, 18 COM3, 19 COM4, 20 COM5, 21 COM6, 22 COM7, 23 COM8, 24 COM9, 25 COM10, 26 COM11, 27 COM12, 28 COM13, 29 COM14, 30 COM15, 31 COM16, 32 COMICN1,2
0, 1, 1, 0
Page6
0, 1, 1, 1 1, 0, 0, 0 Column Address
Page7
Page8
00 01 02 03 04 05 06 07.............. 3F 40 ...... 7E 7F
COMICN1,2
7F 7E 7D 7C 7B 7A 79 78..............
.... .... ...... 01 00
SEG Pin
1234567
8...............
.... .... ...... 127128
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LCD Drive Output Waveform (Waveform B) The following is an example of how the common and segment drivers may be connected to a LCD panel.
1/17 Duty Common Output Pin 1/33 Duty Common Output Pin 1/33 Duty Right/Left Alternate Output Common Output Pin
12 17 18 1 1 2 1
3 19 3 2
.... .... ....
16 32 32 32
COM ICN 1,2
1 17 1 1
2 18 2 17
3 19 3 2 M ....
16 32 32 32
COM ICN 1,2
1,2 1,2
1,2 1,2
M
COM1
V5 V4 V3 V2 V1 VSS V5 V4 V3 V2 V1 VSS
COM2
SEG1
V5 V4 V3 V2 V1 VSS
SEG2
V5 V4 V3 V2 V1 VSS
COM1 - SEG1
V5 V4 V3 V2 V1 VSS -V1 -V2 -V3 -V4 -V5
COM1 - SEG2
V5 V4 V3 V2 V1 VSS -V1 -V2 -V3 -V4 -V5
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Examples of External Bias Resistor Connection vs LCD Drive Waveform
1. 1/2 Bias SEG Waveform M Rd Rd V5=V2 V1=V4 V3=VSS SEG Waveform M M COM Waveform M M Re3 = (Re1 + Re2) Re1=Re3 0 1 Bias = = SEG Waveform V5 V4=V2 V1=V3 VSS SEG Waveform M M COM Waveform M M RC2 + RC3 =RC1 RC2 = RC1 0 1 Bias = = RC1 RC1+ RC2+ RC3 +RC2 +RC1 1 3+ M M COM Waveform M M Re1+ Re2 Re1+ Re2+ Re3 +Re2 +Re1 1 2+ M COM Waveform M M
2. 1/2 to 1/3 Bias V5 V2 V4 V1 V3 VSS 3. 1/3 Bias
Re1 Re2 Re3 Re2 Re1
Rd Rd Rd
4. 1/3 to 1/4 Bias V5 RC1 RC2 RC3 RC2 RC1 V4 V2 V3 V1 VSS 5. 1/4 Bias V5 V4 V2=V3 V1 VSS
SEG Waveform M M
COM Waveform M M
Rb Rb Rb Rb
6. 1/4 Bias or more V5 V4 V3 V2 V1 VSS
SEG Waveform M M
COM Waveform M M Ra2 = Ra1 0 Bias = = Ra1 Ra1+ Ra1+ Ra2 +Ra1 +Ra1 1 4+
Ra1 Ra1 Ra2 Ra1 Ra1
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Absolute Maximum Ratings
Parameter Supply voltage LCD drive voltage 1 LCD drive voltage 2 Input voltage Output voltage Operating temperature range Storage temperature Chip range TAB Note 1 Symbol VDD V5 V1, V2, V3, V4 VIN VOUT Topr Tstg Ratings -0.4 to +6.0 -0.4 to +12 -0.4 to V5 -0.4 to VDD+0.4 -0.4 to VDD+0.4 -30 to +85 -55 to +125 -55 to +100 VSS = 0.0V Unit V V V V V C C
Note 2 Note 3
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. When connecting a bias resistor externally, set the LCD power supply voltage so that the state is changed to V5 VDD.
DC Characteristics
1. Electrical Characteristics
(Unless otherwise specified: VDD = +5.0 0.5V, VSS =0V, Ta = -30 to 85C)
Parameter Operating Voltage LCD Drive Voltage
High-level Input Voltage Low-level Input Voltage High-level Output Voltage
Symbol VDD V5 V1, V2 V3, V4 VIH VIL VOH1 VOH2
Conditions When using an external LCD Power supply VDD=+2.4 to +4.5V VDD=+5.0 0.5V VDD=+2.4 to +4.5V VDD=+5.0 0.5V IOH=-0.5mA, VDD=+2.4 to+4.5V IOH=-I.0 mA IOH=-50A, VDD=+2.4 to+4.5V IOH=-120A IOL=0.5mA, VDD=+2.4 to +4.5V IOL=1.0mA IOL=50A VDD=+2.4 to +4.5V IOL=120A VDD=+2.4 to +5.5V VDD=+2.4 to +5.5V Ta=25C, V5=+8.0V 1/5 Bias
External LCD power supply is used: During LC display V5=+8.0 V Rf= 1 M
Min. +2.4 +2.7 VSS 0.8xVDD 0.8xVDD VSS VSS 0.8xVDD 0.8xVDD 0.8xVDD 0.8xVDD -1.0 -3.0 11 15 10
Typ. 3.0 0.05 20.0 150 300 16 18 -
Max. +5.5 +11 V5
Unit V V V
Note 1 2 3 3 4 OSCO 5 4 OSCO 5 6 7 8 9 10 11 12
Low-level Output Voltage
VOL1 VOL2
Input Leakage Current Output Leakage Current LCD Driver ON Resistor Standby Current Operating Current
IILEAK IOLEAK RON IS ISS1 lSS2
VDD V VDD 0.2xVDD V 0.3xVDD V V 0.2xVDD V 0.2xVDD 0.2xVDD V 0.2xVDD 1.0 A 3.0 A 5.0 5.0 30.0 450 21 22 K A A A KHz s
Oscillating Frequency Wait Time
fOSC tR
During access: tcyc=200 KHz VDD=+3.0 0.3 V During access: tcyc=200 KHz Rf=1.0M VDD=+3.0V Rf=1.0M VDD=+5.0V
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2. LCD Power Supply Circuit Electrical Characteristics
(Unless otherwise specified: VDD = +2.4V to +5.5V, VSS = 0V, Ta = -30 to 85C)
Parameter Operating Voltage Boosting Output Voltage LCD Supply Circuit Operating Voltage LCD Driver Operating Voltage Built-in LCD Circuit Current Consumption External LCD Power Supply Used: LCD Drive Current Consumption Reference Voltage Reference Current LCD Drive bias voltage (1/4 bias)
Symbol VDD VOUT
Conditions
Min. +2.4
Typ. -
Max. +5.5 +11.0 +11.0 +11.0 +11.0 +11.0
Unit V V
Note 13
V5
Triple boosting: Up to VDD=3.6V Double boosting: Up to VDD=5.5V 1/4 Bias 1/5 Bias 1/6.7 Bias
+4.0 +4.5 +5.5 +2.7
V
14
VLCD VOUT=+10.0 V Double Boosting VDD=+5.0 V V5=8.0V 1/5 Bias Osc. Frequency : 18 KHz V5=8.0V 1/5 Bias VREF=+0.01%/C VREF=-0.13%/C
V
15
ISSL
-
+90
+200
A
16
lV5
+2.0 +1.3 1.5 1/4*V5-0.1 2/4*V5-0.1
+30 +2.2 +1.5 2.5 1/4*V5 2/4*V5 2/4*V5 3/4*V5 1/5*V5 2/5*V5 3/5*V5 4/5*V5
+75 +2.4 +1.7 4.0
1/4*V5+0.1 2/4*V 5+0.1 2/4*V 5+0.1 3/4*V 5+0.1 1/5*V 5+0.1 2/5*V 5+0.1 3/5*V 5+0.1 4/5*V 5+0.1
A
17
VREF IREF V1 V2 V3 V4 V1
Ta=25C
V A
18 19
Fine adjustment data (1111) Ta=25C
V5=+4.0V to +11.0V
2/4*V5-0.1 3/4*V5-0.1 1/5*V5-0.1 2/5*V5-0.1
LCD Drive bias voltage (1/5 bias)
V2 V3 V4 V1 V5=+4.5V to +11.0V
3/5*V5-0.1 4/5*V5-0.1
V
20
1/6.75*V5-0.1 1/6.75*V5 1/6.75*V 5+0.1 2/6.75*V5-0.1 2/6.75*V5 2/6.75*V 5+0.1
LCD Drive bias voltage (1/6.75 bias)
V2 V3 V4 V5=+5.5V to +11.0V
4.75/6.5* V5-0.1 5.75/6.75* V5-0.1
4.75/6.75* V5 5.75/6.75* V5
4.75/6.75* V5+0.1 5.75/6.75* V+0.1
3. References Parameter Input Pin Capacity Symbol CIN Conditions Ta=25C Min. Typ. 5 Max. 8 Unit pF Note 3
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Notes: Sharp variation in the supply voltage or input signal voltage due to strange noises may lead to a malfunction of the IC. Supply stable supply voltage and input signal voltage. If you change the level of the supply voltage intentionally, a malfunction may occur. Never change the level of the supply voltage. 2. When the external bias voltage is input, V5V4, V3, V2, V1VSS, V5VDD. There is no limitation for determining the voltage level of V1, V2, V3, and V4. 3. Pins A0, CS , E, R/W, C68/80, P/S, OSCI, FNC1 and FNC2. Pins D0 to D7 during display data write and command input. Fully swing the levels VIH and VIL of the input signal within the range of power supply voltage so that the state is VIH =VDD, VIL=VSS. When the level of VIH and VIL is the middle level of the supply voltage, the through current flowing through the input pin and the current consumption may be increased. 4. Pins D0 to D7 during read. 5. Pins A0 CS , E, R/W, C68/80, P/S, OSCI, FNC1 and FNC2. 6. Pins D0 to D7 during write and high-impedance. 7. ON resistance between LCD drive output pins (SEG1 to SEG128, COM1 to 32, COMICN1, and 2) and LCD drive bias voltage pins (VI, V2, V3, V4). Using the external LCD power supply, measure the resistance at a 0.1-V difference from the LCD drive output pin after applying 1/2 voltage of V5 to the LCD drive bias voltage pin. 8. Power save state. When turning the input pin to "Floating," the through current flows and will eventually the power save effect may be reduced. 9. Shows the current consumption during display including CR oscillation. It does not include the current consumed by the booster, LCD supply voltage adjustment circuit, voltage regulator, LCD bias resistor when using the external LCD power supply. The LCD drive output pin is no load. The current consumed by the LCD panel and wiring capacitor is not included. Measure it without access from the MPU. The current consumed by the external LCD power supply and external bias resistor and other is not included. 10. The current consumption while the checkered pattern display data are being written from the MPU. The CR oscillation is measured while the CR oscillating circuit stops. The voltage level of the input signal is the VIH=VDD and VIL=VSS. When the input signal voltage is in the middle level, the current consumption may be increased. When the display data is written from the MPU during display, the state is changed to ISS1+lSS2. 11. Shows the standard value at oscillating resistor 1M. Determine appropriate oscillating frequency so as not to be in synchronization with the frame frequency and other frequency such as the fluorescent lamps. 12. Shows the wait time from when the power voltage rises to 80 of the specified voltage to when the command input becomes available. 13. The operating voltage range of the booster. 14. Shows the operating voltage range of the LC voltage adjustment circuit, voltage follower, and LCD bias resistor. The operating voltage range differs depending upon each bias setting value. To adjust V5 with the LCD voltage adjustment circuit, it is necessary to set the voltage within the bias voltage. IV5I - IVOUT I 0.2V. 15. The operating voltage range of the LCD driver after the voltage follower functions. Also, it shows the voltage range of V1 to V5 supplied from the external LCD power supply circuit. 16. Shows the value of the current consumed by the booster, LCD voltage adjustment circuit, voltage follower, LCD bias resistor, and LCD driver. It does not include the value IRREG=V5/(R1+R2+R3) of the current flowing through external resistors R1, R2, and R3. Set the command fine adjustment data to 1000. Outputs the checkered patterns from the LCD drive output pin. The pin is measured at "Open." Current consumption of the IC during display is ISSL+lSS1. 17. The built-in LCD power supply circuit stops when FNC1 and 2 are "H." Current consumption only for the LCD driver. Outputs the checkered patterns from the LCD drive output pin. The pin is measured at "Open." Current consumption of the IC during display is IV5+ lSS1. When using the external power supply, stop the built-in power supply circuit which does not need to be operated with pins FNC1 and 2 to prevent the IC from being broken due to a shorting of the internal power supply. 18. The reference voltage differs depending upon the temperature coefficient selected with the corresponding command. 19. Constant current which flows into the LCD Voltage Command Fine Adjustment Circuit of the IC, for the Fine adjustment data (1111). Increasing the Fine adjustment data by 1 bit, V5 increases by Rb x IREF/15. 20. For the Chips deliveries, chips are delivered after they satisfy their LCD drive bias voltages are 0.08V in the delivery testing at 25C. 1.
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Timing Characteristics
1. Parallel Interface 1.1 68-Series MPU Read/Write Timing Interface Characteristics 68-Series MPU Read/Write Timing Characteristics Signal A0 CS , R/W D0 to D7 Symbol tCYC6 tAH6 tAW6 tDS6 tDH6 tACC6 tOH6 tEW Designation System Cycle Time Address Hold Time Address Setup Time Data Setup Time Data Hold Time Access Time Output Disable Time Enable Pulse Width Conditions (Ta=-30 to 85C, VDD=+5V10%) Min. 500 20 20 80 20 10 100 80 Max. Unit Note
E
CL=15 pF CL=15 pF READ WRITE
90 60 -
ns
68-Series MPU Read/Write Timing Characteristics Signal A0
CS , R/W
(Ta=-30 to 85C, VDD=+3V10%) Conditions Min. 1000 40 40 160 40 10 200 160 Max. 180 120 Unit Note
D0 to D7
Symbol tCYC6 tAH6 tAW6 tDS6 tDH6 tACC6 tOH6 tEW
Designation System Cycle Time Address Hold Time Address Setup Time Data Setup Time Data Hold Time Access Time Output Disable Time Enable Pulse Width
ns
E
CL=15 pF CL=15 pF READ WRITE
Note : * Rise/fall time of the input signal is 15 nsec or less. * Timing is specified at 20% or 80% of the signal waveform.
tCYC6
E
tAW6 tEW
R/W
tAH6
A0, CS
tDS6
D0 to D7 (WRITE) DB0 to DB7 (READ)
tACC6
tDH6
tOH6
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1.2 80-Series MPU Read/Write Timing Characteristics 80-Series MPU Read/Write Timing Characteristics Signal A0 CS R/W, E Symbol tAH8 tAW8 tCYC8 tCC8 tDS8 D0 to D7 tDH8 tACC8 tOH8 Designation Address Hold Time Address Setup Time System Cycle Time Control Pulse Width Data Setup Time Data Hold Time E Access Time Output Disable Time CL=15 pF CL=15 pF 10 Conditions (Ta=-30 to 85C, VDD=+5V10%) Min. 20 20 500 100 80 20 90 60 Max. ns Unit Note
80-Series MPU Read/Write Timing Characteristics When VDD=+3V Signal A0 CS R/W, E Symbol tAH8 tAW8 tCYC8 tCC8 tDS8 D0 to D7 tDH8 tACC8 tOH8 Designation Address Hold Time Address Setup Time System Cycle Time Control Pulse Width Data Setup Time Data Hold Time E Access Time Output Disable Time CL=15 pF CL=15 pF Conditions
(Ta=-30 to 85C, VDD=+3V10%) Min. 40 40 1000 200 160 40 10 Max. 180 120 ns Unit Note
Note : * Rise/fall time of the input signal is 15 nsec or less. * Timing is specified at 20% or 80% of the signal waveform.
tAH8
A0, CS
tAW8 tCYC8 tCC8
R/W, E
tDS8
tDH8
D0 to D7 (WRITE)
tACC8 tOH8
D0 to D7 (READ)
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2. Serial Interface
Serial Interface Timing Characteristics Signal
CS
(Ta=-30 to 85C, VDD=+5V10%) Designation Conditions Min. 50 400 120 200 120 50 500 200 200 CL=15 pF CL=15 pF 10 90 60 1 ns Max. Unit Note
Symbol tCSS tCHS tASS tAHS tDSS tDHS tCYCS tCLLS tCLHS tDDS tOHS
Chip Select Setup Time Chip Select Hold Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Clock Cycle Time Clock L Time Clock H Time Data Delay Time Data Disable Time
A0, R/W D0 (SDI) D1 (SCLK) D2 (SDO)
Serial Interface Timing Characteristics Signal
CS
(Ta=-30 to 85C, VDD=+3V10%) Conditions Min. 100 800 240 400 240 100 1000 400 400 10 Max. Unit Note
A0, R/W D0 (SDI) D1 (SCLK) D2 (SDO)
Symbol tCSS tCHS tASS tAHS tDSS tDHS tCYCS tCLLS tCLHS tDDS tOHS
Designation Chip Select Setup Time Chip Select Hold Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Clock Cycle Time Clock L Time Clock H Time Data Delay Time Data Disable Time
ns
CL=15 pF CL=15 pF
180 120
1
Note : 1. D2(DSO) is high-impedance at the rising edge of the CS . 2. Rise/fall time of the signal is 15 nsec. or less 3. Timing is specified at 20% or 80% of the signal waveform.
Serial Interface Read/Write Timing Characteristics
CS
tCS tCHS
A0
tASS
R/W
tCYCS
D1 (SCLK) D0 (SDI) D2 (SDO)
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tCLLS tCLHS tDSS tDHS
tAHS tOHS
tDDS
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Examples of Applications of LCD Power Supply
. When Using a Built-in LCD Power Supply Circuit (Triple Boosting) VDD Rf OSC OSC2 VDD VSS C1+ C1C2+ C2VOUT V5 VCNT
C
C C C C External Boosting Power Supply
. When Using an External Boosting Power Supply Rf OSC OSC2 VDD VSS C1+ C1C C2+ C2R1
C
C C C C
VDD
VSS C C C R1 R2 R3 VSS
VSS
R2 R3 VSS FNC1 FNC2 VSS
VOUT V5 VCNT VSS V1 V2 V3 V4 VDD FNC1 FNC2 VSS
VSS V1 V2 V3 V4
. When Using an External Regulator Rf OSC OSC2 VDD VSS C1+ C1C
External Regulator
. When Using an External LCD Power Supply Rf OSC OSC2 VDD VSS C1+ C1C2+ C2VOUT VCNT VSS V1 V2 V3 V4 V5 VLC
VDD
VDD
VSS
VSS
C2+ C2VOUT V5 VCNT
VSS VDD FNC1 FNC2
C
FNC1
VSS VDD
VSS
C C C C
VSS V1 V2 V3 V4
FNC2
Reference C : 1.0F C1 : 0.47F C2 : 0.1F C3 : 0.01F
Capacitor C3 connected to V3 pin is recommended 0.01F
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* Booster Capacitor Connection
Tripler
Doubler
VSS C1
VS C1-
VSS C1
VS C1C1 Open C1+ C2C2+ VOUT
C1+ C C1 C2+ VOUT C2-
Reference C : 1.0F C1 : 0.47F
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Examples of Connection to LCD Panels
1. 1/17 Duty 17 X 128 Panel
. COM1 to 16 are used: Icon 1 ....
. COM17 to 32 are used: Icon 1 ....
LCD17 X 128
1........128 SE
COM ICN2
LCD17 X 128
Icon 1........128 SE
COM ICN2 A31W33128 COM ICN1
16
16 Icon
COM 1 to 16
A31W33128 COM ICN1
COM 17 to 32
2. 1/33 Duty 17 X 256 Panel
Icon 1 16 1........128 .... SE
COM ICN2 COM 1 to 16 A31W33128 COM ICN1
129........256 17 ....
LCD17 X 256
32 Icon
COM 17 to 32
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Examples of Connection to LCD Panels (continued)
3. 1/33 Duty 33 X 128 Panel
3.1 Normal Common Output
Icon 1 16 ....
COM 1 to 16
LCD 33 X 128
1........128 SE
COM ICN2 A31W33128 COM ICN1
17 32 Icon ....
COM 17 to 32
Output in a numerical order of common pin Nos.
3.2 Common Right/Left Alternate Output
Icon 1 3 .... Uneven-Numbered Common Line 29 31
LCD 33 X 128
1........128 SE
COM ICN2
2 4 30 32 Icon .... Even-Numbered Common Line
COM 1 to 16
A31W33128 COM ICN1
COM 17 to 32
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A31W33128 Series
Ordering Information
Part No. A31W33128C A31W33128T Package COG TCP
PRELIMINARY
(December, 2000, Version 0.1)
33
AMIC Technology, Inc

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Price & Availability of A31W33128

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